1. Field of the Invention
The present invention relates to a synchronous circuit and more particularly a synchronous circuit having a circuit for detecting a phase error at a center of reference signal.
2. Description of Related Art
A conventional synchronous circuit is shown in FIG. 5 used to reproduce a clock signal of a television signal. As shown in FIG. 5, the conventional synchronous circuit comprises a phase error detector 1, a voltage controlled oscillator (VCO) 2 and a smoothing capacitor 3. The phase error detector 1 is constructed with a multiplier circuit supplied with. a horizontal synchronizing signal (referred to as "H-sync signal", hereinafter) synchronously separated from the television signal and an output signal of the VCO 2. The smoothing capacitor 3 smooths an output current of the phase error detector 1 and the VCO 2 oscillates at a frequency controlled by a phase error signal obtained by converting the output current of the phase error detector 1 into a voltage by the smoothing capacitor 3.
Describing an operation of the conventional synchronous circuit, a discharge current or a suction (charge) current flows on an output side of the phase error detector 1 depending upon the polarity of an output of the VCO 2 for only a time period in which the H-sync signal is in an active state. By smoothing this current by the smoothing capacitor 3, a potential difference proportional to a difference in phase between a center of the H-sync period and an edge of the output waveform of the VCO 2 is obtained as a control signal for the VCO 2.
When the edge of the output waveform of the VCO 2 is precedent to the center of the H-sync period, the suction charge becomes larger than the discharge charge on the output side of the phase error detector 1, so that the control voltage of the VCO 2 is reduced to thereby lower the oscillation frequency of the VCO 2 and hence delay the phase of the output waveform of the VCO 2.
On the contrary, when the edge of the output waveform of the VCO 2 is succeeding to the center of the H-sync signal period, the discharge current becomes larger than the suction current on the output side of the phase error detector 1, so that the control voltage of the VCO 2 is increased to thereby advance the phase of the output waveform of the VCO 2. In this manner, a phase locked loop (PLL) is formed, and the clock signal synchronized with the H-sync signal is obtained.
Now, an operation of the phase error detector will be described in detail with reference to FIG. 5 showing the circuit connection and FIG. 6 showing potentials and currents at respective points of the circuit.
When the H-sync of positive logic shown in FIG. 6 is input from a synchronizing signal separator circuit (not shown) to an REF terminal of the phase error detector 1 as shown in FIG. 5, a collector current I (ampere) of a transistor Q1 having a base connected to the REF terminal flows in only the H-sync period and the collector current is cut off in other period than the H-sync period.
When the output of the VCO 2 is in low state in the H-sync period, a current i1 flowing through a transistor Q2 becomes I amperes, otherwise, i1=0. Similarly, when the output of the VCO 2 is in high state in the H-sync period, a current i2 flowing through a transistor Q3 becomes I amperes, otherwise, i2=0.
That is, the output current i.sub.out of the phase error detector 1 becomes I amperes in the discharge direction only when the output of the VCO 2 is in low state within the H-sync period and becomes I amperes in the suction direction when the output of the VCO 2 is in high state within the H-sync period and there is no current flows in other period than the H-sync period.
When such output current i.sub.out of the phase error detector 1 is supplied to the capacitor 3, a charge/discharge curve thereof becomes as depicted by V.sub.ctr1 shown in FIG. 6 and the potential difference .DELTA.V proportional to the difference in phase between the edge of the output signal of the VCO 2 and the center of the H-sync period. The above can be represented by the following equation (1): EQU .DELTA.V={I.times.t1-I.times.(T-t1)}/C={2I.times.t1-I.times.T}/C EQU t2=t1-T/2 EQU .thrfore..DELTA.V=2I/C.times.t2 (1)
where .DELTA.V . . . change of the control signal V.sub.ctr1 of the VCO 2
I . . . collector current of the transistor Q1 in the H-sync period PA1 T . . . H-sync period PA1 t1 . . . delay (phase difference) from a front edge of the H-sync period to a front edge of the output signal of the VCO 2 PA1 t2 . . . phase delay (phase difference) from the center of the H-sync period to the front edge of the output signal of the VCO 2 PA1 C . . . capacitance of the smoothing capacitor 3, and, from the operating condition of the phase error detector 1, t1&lt;T, -T/2&lt;t2&lt;T/2. PA1 a discrete time oscillator responsive to an output of a loop filter as a control input, PA1 a phase error detector responsive to a reference signal alternating between two levels about a first threshold value and an output data of the discrete time oscillator, and PA1 a loop filter responsive to the output data of the phase error detector.
The oscillation frequency of the VCO 2 is controlled by the control signal V.sub.ctr1 and, when the center phase of the H-sync period is advanced to the front edge phase of the output signal of the VCO 2 (t2&gt;0), .DELTA.V becomes positive to increase the control signal V.sub.ctr1 to thereby advance the front edge phase of the output signal of the VCO 2.
Therefore, in the normal state, t2.apprxeq.0 second, that is, .DELTA.V.apprxeq.0 volt, and the VCO 2 oscillates in synchronism with the H-sync signal.
However, since the phase error detector 1 shown in FIG. 5 obtains the phase error between the reference signal and the H-sync signal by using the analog multiplier circuit, the phase error signal is saturated and becomes 1 or 0 constantly for the phase error exceeding the period of the H-sync signal, although the error signal becomes proportional to the phase error when the phase error is within the period of the H-sync signal.
That is, the loop gain when the phase error exceeding the period of the H-sync signal is input becomes 0 and the synchronizing operation is not performed until the phase error becomes inside of the period of the H-sync signal. As a result, the response characteristics of the loop are degraded during a period from the asynchronized state after the power source is turned on to the time at which the phase is locked or during a period from a time at which the phase is unlocked for some external reason to a time at which the phase is locked again.
Further, since the smoothing circuit connected to the output side of the phase error detector 1 is realized by the resistance element and the capacitance element which are outside the integrated circuit, the temperature characteristics of the phase error detector 1 may be different from that of the smoothing circuit (smoothing capacitor 3) and the manufacturing variation of the phase error detector 1 is also different from that of the smoothing circuit, so that the temperature characteristics and the variation may be introduced to the PLL loop gain.